As modern electronic devices become denser and operate on lower voltages than in the past, the circuits in those devices become more and more sensitive to simultaneous switching noise and heat caused by excessive switching. The simultaneous switching noise is caused by logic that switches states (from. 0 to 1 or from 1 to 0) and as they switch, the power signal is shorted to ground for a brief period of time. Because this switching period is very brief,—it is not of a great concern in a circuit design if just a small portion of the logic switches; however, for a very dense design with hundreds of millions or even billions of logic gates, the total effect of the switching is massive if a large number of these logic gates switch at nearly the same instance in time. The short-lived shorts from the power (Vdd signals) to the ground cause the ground signals in the circuit to be pulled up from the ground voltage toward the Vdd voltage (e.g., 0.8V up to 1.5V in most current chip technologies). Simultaneously, the Vdd voltage tends to be pulled down toward the ground voltage. As the ground and Vdd voltages move closer to each other, the circuits begin to fail. The fluctuation of the voltage between the Vdd and ground signals is called “power rail noise” and is often referred to in the literatures as “simultaneous switching noise.”
When simultaneous switching noise affects a logic design during a test, the test responses are neither predictable nor reliable. For example, a perfectly good device may appear to be failing a test because the switching activity is too high during the test. The yield may be very low and impact the profit margin for the device being manufactured.
In addition to simultaneous switching noise, high switching activity also generates excessive heat on the device. When more heat is generated than can be dissipated from the device during a given time period, a physical damage may occur to the device. Although both the power rail noise and heat are byproducts of excessively high switching activity within the device, the heat dissipation problem can be dealt with by slowing down the operational speed of the device so that the switching per unit of time is reduced. This reduces the power that is converted into heat per unit of time allowing more heat to be dissipated over time. Slowing down the operation of a device during a test may reduce the problem of overheating, but it creates other problems such as the elongated test time and/or not being able to test and stress the device at an operational speed. Because the cost of testing is usually in proportion to the amount of time the device is required to be in process on the automated test equipment (ATE), a longer test time translates into higher costs.
Certain techniques for compressing test patterns and applying them to scan chains with reduced data to save test time are known in the art. Prior art techniques compute a compressed test pattern using symbolic expressions associated with scan cells of an integrated circuit and solving a set of linear equations to obtain the compressed test patterns. The symbolic expressions are a linear function of input variables and are concurrently applied while loading the scan cells to address limitations such as seed-length limitations and mutually exclusive times for loading the seed. This prior art technique is useful for solving linear equations (e.g., XOR gates), however, is inadequate for solving equations that are not linear (AND or OR gates) or equations having inputs that are randomly or weightedly clocked. Furthermore, the decompressor is continually clocked to decompress the input variables such that the clock is gated for every scan cycle at each scan chain. However, if the linear equations are determined to be unsolvable for a certain scan cycle, the current test needs to be discarded and a new test must be restarted to apply new test patterns. This is a significant disadvantage.
Another prior art technique utilizes a real-time decoder for decompressing input test stimulus through a combinational or sequential logic linear decompressor. According to prior art test pattern decompression techniques, the output data from the decompressor is generally random and switches at a nominal 50% switching rate, significantly higher than functional switching rates that are typically between 5% and 25%. This translates directly into frequent switching of data values during scan cycles into the scan chains fed by the outputs of the decompressor. Resultantly, the frequent switching of data values generates noise in the power rails and causes excessive heat.
The present teachings described herein provide a method and system for reducing switching activity during scan testing of a logic design. The reduced switching applies during every scan clock cycle when loading new values into scan chains. The reduced switching helps at both reducing power supply noise as well as reducing heat/power dissipation.